Semiconductor device for short-circuiting output terminals of two or more voltage generator circuits at read time and control method for the same

ABSTRACT

According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2009-152642, filed Jun. 26, 2009; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein related generally to a semiconductor deviceapplied to a nonvolatile semiconductor memory device.

BACKGROUND

Recently, the distances between adjacent word lines and between adjacentbit lines are more narrow as the device is semiconductor devices arefurther miniaturized. That is, the distance between memory celltransistors is narrow has decreased. Therefore, for example, if data iswritten into a memory cell transistor in which binary data is held, thethreshold distribution of a memory cell transistor in which data hasbeen already written varies due to variation in the thresholddistribution of a memory cell transistor adjacent to the above memorycell transistor. In the following description, the variation in thethreshold distribution is referred to as a coupling effect. “couplingeffect.”

Therefore, the threshold value of the memory cell transistor is raisedfrom the initial read level and it becomes necessary to transfer ahigher voltage in order to turn on the memory cell transistor. That is,a voltage generator circuit that generates plural voltages is required.In Jpn. Pat. Appln. KOKAI Publication No. H11-134892, voltage generatorcircuits whose current supply rates are different are described.

In this case, if the above high voltage is transferred to the controlgate of a memory cell transistor adjacent to a memory cell transistorbefore the high voltage is transferred to the control gate of the lattermemory cell transistor, gate induced drain leakage (GIDL) will occurbetween the impurity diffusion layer and the memory cell transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a NAND flash memory according to a firstembodiment;

FIG. 2 is a cross-sectional view of the NAND flash memory according tothe first embodiment;

FIG. 3 shows the threshold distribution of a memory cell transistoraccording to the first embodiment;

FIG. 4 is a block diagram of a voltage generator circuit according tothe first embodiment;

FIG. 5 is a block diagram of a voltage generator circuit and controlleraccording to the first embodiment;

FIGS. 6A, 6B show a data read operation of the memory cell transistoraccording to the first embodiment, FIG. 6A showing a first read step andFIG. 6B showing a second read step;

FIG. 7 is a time chart for illustrating a voltage transmission operationat a data read time in the NAND flash memory according to the firstembodiment;

FIG. 8 is a time chart for illustrating a voltage transmission operationat a data read time in the NAND flash memory according to the firstembodiment;

FIG. 9 is a cross-sectional view of the conventional NAND flash memory;

FIG. 10 is a time chart for illustrating a voltage transmissionoperation at a data read time in a NAND flash memory according to amodification corresponding to the first embodiment;

FIG. 11 is a block diagram of a voltage generator circuit and controlleraccording to a second embodiment;

FIGS. 12A, 12B show a data read operation of a memory cell transistoraccording to the second embodiment, FIG. 12A showing a first read stepand FIG. 12B showing a second read step;

FIG. 13 shows a data read operation of the memory cell transistoraccording to the second embodiment; and

FIG. 14 is a time chart for illustrating a voltage transmissionoperation at a data read time in a NAND flash memory according to thesecond embodiment.

DETAILED DESCRIPTION

Next, a first embodiment is explained with reference to the accompanyingdrawings. In the explanation, common reference symbols are attached tocommon portions throughout the drawings.

In general, according to one embodiment, a semiconductor device includesa first voltage generator circuit, a second voltage generator circuit, afirst MOS transistor, and a controller. The first voltage generatorcircuit outputs a first voltage to a first node. The second voltagegenerator circuit outputs a second voltage to a second node. The firstMOS transistor is capable of short-circuiting the first and secondnodes. The controller performs a control operation to short-circuit thefirst and second nodes by turning on the first MOS transistor. Thecontroller controls a period in which the first MOS transistor is keptin the on state based on time.

[First Embodiment]

The semiconductor device according to the first embodiment is explainedwith reference to FIG. 1. The summary of this embodiment is toshort-circuit the output terminals of two or more voltage generatorcircuits that generate various voltages at a read time. Therefore,voltage transfer timings of voltages applied to plural word lines WL areset to the same timing. First, the configuration of the semiconductordevice according to the first embodiment is explained.

In FIG. 1, the semiconductor device according to the first embodiment isshown. As one example, a NAND flash memory is provided. As shown in FIG.1, the NAND flash memory includes a memory cell array 1, row decoder 2,word line control circuit 3, voltage generator circuit 4, senseamplifier 5 and controller 6. First, the memory cell array 1 isexplained.

<Configuration Example of Memory Cell Array 1>

As shown in FIG. 1, the memory cell array 1 includes plural blocks BLK0to BLKs (s is a natural number). Each of the blocks BLK0 to BLKsincludes plural NAND strings 11 including nonvolatile memory celltransistors MT serially connected.

For example, each of the NAND strings 11 includes 64 memory celltransistors MT and select transistors ST1, ST2. The memory celltransistor MT has an FG structure having a charge storage layer (forexample, conductive film) formed above a semiconductor substrate with agate insulating film disposed therebetween, an inter-level insulatingfilm formed on the charge storage layer and a control gate electrodeformed on the inter-level insulating film.

The number of memory cell transistors MT is not limited to 64 and may beset to 128, 256 or 512 and the number is not limitative. Further,adjacent ones of the memory cell transistors MT commonly have the sourceor drain. The memory cell transistors MT are arranged to have thecurrent paths serially connected between the select transistors ST1 andST2. The drain region on one-end side of the series-connected memorycell transistors MT is connected to the source region of the selecttransistor ST1 and the source region on the other end side is connectedto the drain region of the select transistor ST2.

The charge storage layer of the memory cell transistor may be formed ofa conductive film (floating gate) such as a polysilicon film, forexample, but may be formed of an insulating film (MONOS structure). Inthis case, the laminated gate includes a charge storage layer formed ofan insulating film on the gate insulating film, a block layer formed ofa ferroelectric material having a dielectric constant higher than thatof the charge storage layer on the charge storage layer and a controlgate formed on the block layer.

The control gate of the memory cell transistor MT functions as a wordline WL, the drain is electrically connected to a bit line BL and thesource is electrically connected to a source line SL.

The control gate electrodes of the memory cell transistors MT arrangedon the same row are commonly connected to a corresponding one of wordlines WL0 to WL63 and the gate electrodes of the select transistors ST1,ST2 arranged on the same row are commonly connected to select gate linesSGD1, SGS1, respectively. For simplifying the explanation, in thefollowing explanation, the word lines WL0 to WL63 may simply be referredto as word lines WL if they are not separately used. Further, the drainsof the select transistors ST1 arranged on the same column in the memorycell array 1 are commonly connected to a corresponding one of bit linesBL0 to BLn. In the following description, the bit lines BL0 to BLn arereferred to as bit lines BL if they are not separately used (n is anatural number). The sources of the select transistors ST2 are commonlyconnected to the source line SL.

Further, data is simultaneously written into the plural memory celltransistors MT connected to the same word line WL and the unit of thememory cell transistors is called a page. Further, data items of theplural NAND strings 11 are simultaneously erased in the block BLK unit.

<Cross-Sectional View of Memory Cell Array 1>

Next, the cross section of the memory cell array 1 in the blocks BLK0 toBLKs with the above configuration is explained with reference to FIG. 2.FIG. 2 is a cross-sectional view of the NAND string 11 taken along thebit line BL direction in FIG. 1.

As shown in FIG. 2, an n-type well region 101 is formed in the surfacearea of a p-type semiconductor substrate 100. A p-type well region 102is formed in the surface area of the n-type well region 101. A gateinsulating film 104 is formed on the p-type well region 102. Gateelectrodes of memory cell transistors MT and select transistors ST1, ST2are formed on the gate insulating film 104.

The gate electrodes of the memory cell transistors MT and selecttransistors ST1, ST2 are formed with the laminated structure having anFG structure. The laminated structure is obtained by sequentiallyforming a conductive film 105, interlevel insulating film 106 andpolysilicon layer 107 on the gate insulating film 104. The surfaceportion of the polysilicon layer 107 is modified into a metal silicideform.

In the memory cell transistor MT explained above, the gate insulatingfilm 104 functions as a tunnel insulating film. The conductive film 105functions as a floating gate (FG) and the polysilicon layer 107functions as a control gate. The polysilicon layers 107 that areadjacent in the word line WL direction intersecting with the bit line BLdirection in FIG. 1 are commonly connected and function as a controlgate electrode (word line WL). In the following description, theconductive film 105 and polysilicon layer 107 may be referred to as acharge storage layer 105 and control gate 107, respectively.

Further, in the select transistors ST1, ST2, the conductive films 105that are adjacent in the word line WL direction are commonly connected.Then, the conductive films 105 function as select gate lines SGS, SGD.At this time, only the polysilicon layer 107 may function as a selectgate line. In this case, the potentials of the polysilicon layers 107 ofthe select transistors ST1, ST2 are set at a constant potential or setinto a floating state.

In portions of the surface area of the p-well region 102 that liebetween the gate electrodes, n⁺-type impurity diffusion layers 103 areformed. The n⁺-type impurity diffusion layer 103 is commonly used by theadjacent transistors and functions as a source (S) or drain (D).Further, a region between the adjacent source and drain functions as achannel region used as an electron moving region. The gate electrodes,n⁺-type impurity diffusion layers 103 and channel regions configuretransistors used as the memory cell transistors MT and selecttransistors ST1, ST2.

On the p-type semiconductor substrate 100, an inter-level insulatingfilm 108 is formed to cover the memory cell transistors MT and selecttransistors ST1, ST2. In the inter-level insulating film 108, a contactplug CP2 that reaches the n⁺-type impurity diffusion layer (source) 103of the select transistor ST2 on the source side is formed. In thesurface area of the inter-level insulating film 108, a metalinterconnection layer 109 connected to the contact plug CP2 is formed.The metal interconnection layer 109 functions as a part of the sourceline SL. In the inter-level insulating film 108, a contact plug CP3 thatreaches the n⁺-type impurity diffusion layer (drain) 103 of the selecttransistor ST1 on the drain side is formed. A metal interconnectionlayer 110 connected to the contact plug CP3 is formed in the inter-levelinsulating film 108. An inter-level insulating film 111 is formed on theinter-level insulating film 108. An inter-level insulating film 112 isformed on the inter-level insulating film 111. A metal interconnectionlayer 113 is formed on the inter-level insulating film 112. The metalinterconnection layer 113 functions as a bit line BL. A contact plug CP4whose upper surface contacts with the metal interconnection layer 113and whose bottom surface contacts with the metal interconnection layer110 is formed in the inter-level insulating films 111, 112. The contactplugs CP3, CP4 and metal interconnection layer 110 function as a contactplug CP1. Further, an insulating film 114 is formed on the metalinterconnection layer 113.

<Threshold Distribution of Memory Cell Transistor MT>

Next, the threshold distribution of the memory cell transistor MT isexplained with reference to FIG. 3. FIG. 3 is a graph showing thethreshold distribution on the abscissa and the number of cells of thememory cell transistors MT on the ordinate.

As shown in FIG. 3, each of the memory cell transistors MT can holdbinary (2-level) data (one-bit data), for example. That is, the memorycell transistor MT can hold two types of data items of “1” and “0” in anorder starting from the lowest threshold voltage Vth.

The threshold voltage Vth0 of “1” data in the memory cell transistor MTis set to satisfy the relationship of Vth0<V01. The threshold voltageVth1 of “0” data is set to satisfy the relationship of V01<Vth1. Thus,the memory cell transistor MT can hold 1-bit data of “0” data and “1”data according to the threshold voltage.

The threshold voltage varies by injecting charges into the chargestorage layer. Further, the memory cell transistor MT may be formed tohold data of four or more values.

<Row Decoder 2>

Next, the row decoder 2 is explained with reference to FIG. 1 again. Therow decoder 2 includes a block decoder 20 and n-channel MOS transistors21 to 23. The block decoder 20 decodes a block address supplied from thecontroller 6 at the data write operation time, read operation time anderase time. Then, the block decoder 20 selects one of the blocks BLKbased on the decoded result. That is, the block decoder 20 selects theMOS transistors 21 to 23 corresponding to the block BLK that containsthe selected memory cell transistor MT and turns on the MOS transistors21 to 23 via a control line TG.

At this time, a block select signal is output from the block decoder 20.The block select signal is a signal used to permit the row decoder 2 toselect one of the plural memory blocks BLK0 to BLKs at the data readtime, write time or erase time. As a result, the row decoder 2 selectsthe row direction of the memory cell array 1 corresponding to theselected block BLK. That is, the row decoder 2 applies voltages suppliedfrom the voltage generator circuit 4 via the word line control circuit 3to the select gate lines SGD1, SGS1 and word lines WL0 to WL63 based onthe select signal supplied from the block decoder 20.

<Word Line Control Circuit 3>

Next, the word line control circuit 3 is explained. In this case, thefunction of the word line control circuit 3 is explained. The word linecontrol circuit 3 transfers various voltages generated from the voltagegenerator circuit 4 to adequate word lines WL assigned by the rowdecoder 2 via the row decoder 2.

For example, it is supposed that the memory cell transistor MT to beread is connected to the word line WL31. In this case, the word linecontrol circuit 3 transfers a voltage corresponding to read data held bythe memory cell transistor MT to the word line WL31. Then, the word linecontrol circuit 3 performs a control operation to transfer a voltagethat turns on the memory cell transistor MT to the word lines WL0 toWL30 and word lines WL32 to WL63 other than the word line WL31.

A signal sgd is transferred to the gate of the select transistor ST1 viathe select gate line SGD1 by means of the word line control circuit 3.Further, a signal sgs is transferred to the gate of the selecttransistor ST2 via the select gate line SGS1 by means of the word linecontrol circuit 3. Each of the signal sgd and signal sgs is a signal inwhich the ‘H’ level is set to voltage VDD (for example, 1.8 [V]) and the‘L’ level is set to 0 [V]. The select transistors ST1, ST2 are turned onby voltage VDD.

<Voltage Generator Circuit 4>

Next, the voltage generator circuit 4 is explained. As shown in FIG. 1,the voltage generator circuit 4 includes a first voltage generatorcircuit 41, second voltage generator circuit 42, third voltage generatorcircuit 43, fourth voltage generator circuit 44 and fifth voltagegenerator circuit 45. The first voltage generator circuit 41 to fifthvoltage generator circuit 45 are explained with reference to FIG. 4.

As shown in FIG. 4, each of the first voltage generator circuit 41 tofifth voltage generator circuit 45 includes a limiter circuit 50 andcharge pump circuit 51. The charge pump circuit 51 generates voltagesrequired for performing, for example, the data write operation, eraseoperation and read operation that are controlled by the controller 6.Each voltage thus generated is output from the node N1 and supplied to,for example, the row decoder 2 of the NAND flash memory via the wordline control circuit 3.

The limiter circuit 50 controls the charge pump circuit 51 according tothe potential of the node N1 monitoring the potential of the node N1.That is, the limiter circuit 50 stops the pumping operation of thecharge pump circuit 51 to drop the potential of the node N1 if thepotential of the node N1 is higher than a preset potential.

On the other hand, if the potential of the node N1 is lower than thepreset potential, the limiter circuit instructs the charge pump circuit51 to perform the pumping operation to raise the potential of the nodeN1.

Next, voltages generated from the first voltage generator circuit 41 tofifth voltage generator circuit 45 are explained. The first voltagegenerator circuit 41 generates voltage VREAD and transfers voltage VREADto unselected word lines at the data read time. Voltage VREAD is avoltage used to turn on the memory cell transistor MT irrespective ofdata to be held.

The second voltage generator circuit 42 generates voltage VREADLA.Voltage VREADLA generated from the second voltage generator circuit 42is transferred to the unselected word line WL adjacent to the drain sideof the selected word line WL via the row decoder 2. Like voltage VREAD,voltage VREADLA is a voltage used to turn on the memory cell transistorMT connected to the unselected word line WL and is set higher thanvoltage VREAD as required. That is, voltage VREADLA may be set lowerthan voltage VREAD. The magnitude of voltage VREADLA is controlled bythe limiter circuit 50.

The third voltage generator circuit 43 generates voltage VCGR at thedata read time. Voltage VCGR is transferred to the selected word lineWL. Voltage VCGR is a voltage corresponding to data to be read from thememory cell transistor MT.

The fourth voltage generator circuit 44 generates voltage VPGM at thedata write time and transfers voltage VPGM to the selected word line WL.Voltage VPGM is a voltage with such magnitude that injects charges ofthe channel in the memory cell transistor MT into the charge storagelayer and the shifts threshold voltage of the memory cell transistor MTto another level.

The fifth voltage generator circuit 45 generates voltage VPASS andtransfers voltage VPASS to the unselected word lines WL. Voltage VPASSis a voltage used to turn on the memory cell transistor MT. If the firstvoltage generator circuit 41 to fifth voltage generator circuit 45 arenot separately used, they are simply referred to as the voltagegenerator circuit 4.

<Sense Amplifier 5>

The sense amplifier 5 senses and amplifies data of the memory celltransistor MT read to the bit line BL at the data read time. Morespecifically, the sense amplifier 5 precharges the bit line BL tovoltage VDD. Then, the sense amplifier 5 senses a voltage (or current)of the bit line BL.

The sense amplifier transfers voltage VDD transferred from the voltagegenerator circuit 4 to the bit line BL at the data write time.

<Control Portion 6>

Next, the controller 6 is explained. The controller 6 short-circuits theoutput terminals of the first voltage generator circuit 41 and secondvoltage generator circuit 42 at the read time. As a result, voltagesoutput from the output terminals of the first voltage generator circuit41 and second voltage generator circuit 42 rise at the same rising rate.

Further, the controller 6 controls the whole operation of the NAND flashmemory. That is, it executes an operation sequence of the data writeoperation, read operation and erase operation based on the address andcommand supplied from a host (not shown).

The controller 6 generates a block select signal/column select signalbased on the address and operation sequence. The controller 6 outputsthe block select signal to the row decoder 2.

<First, Second Voltage Generator Circuits 41, 42 and Short Circuit 7>

Next, configuration examples of the short circuit 7 and the first,second voltage generator circuits 41, 42 explained above are explainedwith reference to FIG. 5. FIG. 5 is a block diagram of the controller 6,short circuit 7, first voltage generator circuit 41, and second voltagegenerator circuit 42.

The controller 6 includes a control unit 60 and local pump 61. The localpump 61 outputs a signal of ‘L’ or ‘H’ level to the short circuit 7according to enable signal EN (indicated by EN in FIG. 5) supplied fromthe control unit 60.

The local pump 61 is connected to a node N3 that is the output terminalof the second voltage generator circuit 42. That is, the local pump 61applies a voltage to the gate electrode of a MOS transistor 71 with thepotential of the node N3 used as a reference voltage. In other words,the voltage applied to the gate of the MOS transistor 71 by the localpump 61 is set at least equal to a value that is not smaller than thesum of the reference voltage of the node N3 and the threshold voltage ofthe MOS transistor 71. In this case, if the threshold voltage of the MOStransistor 71 is set to Vth₇₁, a signal of ‘H’ level output from thelocal pump 61 is set to a voltage (voltage Vth₇₁+potential of the nodeN3). The MOS transistor 71 is turned on by the signal of ‘H’ level.

Further, the node N2 is connected to the output terminal of the firstvoltage generator circuit 41 and the node N3 is connected to the outputterminal of the second voltage generator circuit 42 as described before.Extensions of the nodes N2 and N3 are electrically connected to the wordlines WL via the word line control circuit 3 and row decoder 2 describedbefore.

The short circuit 7 includes the MOS transistor 71. The MOS transistor71 is a n-type MOS transistor with a higher withstand voltage than thoseof the MOS transistors 21 to 23. Specifically, the MOS transistor is ann-type intrinsic MOS transistor (that is hereinafter referred to as anI-type MOS transistor).

One end of the current path of the MOS transistor 71 is connected to thenode N2, the other end thereof is connected to the node N3 and the gatethereof is applied with an output of the local pump 61. That is, the MOStransistor 71 is turned on according to an output of the local pump 61to short-circuit the nodes N2 and N3. The potentials of the nodes N2 andN3 are set equal to the same potential if the nodes N2 and N3 areshort-circuited.

The MOS transistor 71 may be an n-type depletion MOS transistor (that ishereinafter referred to as a D-type MOS transistor) with high withstandvoltage or an n-type enhancement MOS transistor (that is hereinafterreferred to as an E-type MOS transistor) with high withstand voltage.However, it is more preferable to use the I-type MOS transistor. Thereason is that the on/off switching speed is higher if the absolutevalue of the threshold voltage is smaller.

Next, the threshold characteristics of the E-type, E-type and I-type MOStransistors are explained. The threshold voltage of the E-type MOStransistor is the highest among them and is positioned on the positiveside with respect to the threshold voltages of the D-type and I-type MOStransistors.

That is, in a case where the threshold voltage thereof is set to Vth_(E)and when the potential of the node N2 or N3 is set to 0 [V], the MOStransistor 71 is turned on if a voltage higher than or equal to voltageVth_(E) is applied to the gate thereof. Further, if a voltage is lowerthan voltage Vth_(E) is applied, the MOS transistor 71 is turned off.

The threshold voltage of the D-type MOS transistor is the lowest and ispositioned on the negative side. That is, in a case where the thresholdvoltage thereof is set to Vth_(D) and when the potential of the node N2or N3 is set to 0 [V], the MOS transistor 71 is turned on if a voltagehigher than or equal to Vth_(D) is applied to the gate thereof. Further,if a voltage that lies on the negative side with respect to voltageVth_(D) is applied, the MOS transistor 71 is turned off.

The threshold voltage of the I-type MOS transistor is set between thethreshold voltages of the D-type and E-type MOS transistors and ispositioned between 0 [V] and voltage Vth_(D). It is supposed that thethreshold voltage thereof is set to Vth_(I) and the potential of thenode N2 or N3 is set to 0 [V]. In this case, if a voltage higher than orequal to Vth_(i) is applied to the gate thereof, the MOS transistor 71is turned on. Further, if a voltage that lies on the negative side withrespect to voltage Vth_(i) is applied, the MOS transistor 71 is turnedoff.

The local pump 61 according to this embodiment generates a positivepotential. For this reason, it is preferable to use an I-type MOStransistor with a low threshold voltage as shown in FIG. 5 as a MOStransistor that can be rapidly switched from the off state to the onstate and maintain the MOS transistor 71 in the on state when the gatepotential is set at 0 [V] without driving the local pump 61.

Further, if the I-type MOS transistor is used, the MOS transistor 71 isturned off by applying a back-bias voltage of approximately 2 [V] to thenode N2 or N3.

If the D-type MOS transistor is used, the MOS transistor 71 is turnedoff by applying a back-bias voltage of approximately 4 [V] to the nodeN2 or N3. If the MOS transistor 71 is used as the E-type MOS transistor,it is unnecessary to apply the above back-bias voltage.

<Read Operation of NAND Flash Memory>

Next, the read operation of the NAND flash memory is explained withreference to FIGS. 6A and 6B. FIGS. 6A, 6B are views showing a state inwhich data is read from the memory cell transistor MT corresponding toan Nth (N is a natural number) word line WL with much attention paid tothe memory cell transistor MT in the cross-sectional view of the memorycell array 1 explained in FIG. 2. That is, the Nth word line WL is usedas a selected word line WL.

<Step 1>

First, it is supposed that data of the memory cell transistor MT whosecontrol gate 107 is connected to a selected word line WLN is read. Inthis case, the third voltage generator circuit 43 transfers voltage VCGRto the memory cell transistor MT that is adjacent to the drain side ofthe selected word line WLN. That is, it transfers voltage VCGR to anunselected word line WL(N+1).

For example, in the case of N=31, the third voltage generator circuit 43transfers voltage VCGR to the word line WL32 adjacent to the selectedword line WL31. As a result, it becomes possible to grasp the thresholddistribution of the memory cell transistor MT corresponding to the wordline WL32. That is, even if the threshold distribution of the memorycell transistor MT is deviated from the initially designed thresholddistribution, the threshold distribution of the memory cell transistorMT can be grasped by performing the above read step.

In other words, since voltage VCGR is set to a voltage corresponding todata to be read from the memory cell transistor MT, the thresholddistribution of the memory cell transistor MT can be confirmed by use ofthe value of voltage VCGR that turns on the memory cell transistor MT.

A value of voltage VREADLA generated by the second voltage generatorcircuit is set by use of the value of voltage VCGR. In this case, it issupposed that voltage VREADLA is set equal to voltage (VREAD±α).

If the threshold distribution of the memory cell transistor MT is high,voltage VREADLA=voltage (VREAD+α) and if the threshold distribution islow, voltage VREADLA=voltage (VREAD-α).

<Step 2>

In step 2, voltage VCGR is transferred to the control gate 107 of thememory cell transistor MT connected to the selected word line WLN. Atthis time, the second voltage generator circuit 42 transfers voltageVREADLA to the word line WL(N+1) adjacent to the word line WLN.

Further, since N=31 and (N−1)=32 as described above, the second voltagegenerator circuit 42 transfers voltage VREAD to the other word lines WL0to WL30 and word lines WL33 to WL63.

At this time, voltage VREADLA transferred to the word line WL(N+1) isset to a voltage corresponding to the threshold distribution of thememory cell transistor MT whose control gate 107 is connected to theword line WL(N+1) in step 1. As a result, the memory cell transistor MTconnected to the word line WL is turned on and a data read operation isperformed by means of the sense amplifier 5 via the bit line BL (notshown).

<Voltage Transfer Operation at Read Operation Time (First Case)>

Next, the voltage transfer operation at the read operation time of theNAND flash memory is explained with reference to FIG. 7. In this case,it is supposed that voltage VREADLA generated from the second voltagegenerator circuit 42 is higher than voltage VREAD. That is, voltageVREADLA=voltage (VREAD+α).

FIG. 7 is a time chart of enable signal EN applied to the local pump 61,a potential applied to the gate of the MOS transistor 71, signal TG, theon-off state of the MOS transistor 23, potentials of the nodes N2, N3and potentials of the word lines WL.

Further, for the nodes N2, N3 in the drawing, the solid line indicatesthe potential of the node N2 and the broken lines indicate the potentialof the node N3. The timing of the voltage transfer operation iscontrolled by means of the controller 6. In the following description,this is true in all of the embodiments.

<Before Time t0>

As shown in FIG. 7, signal TG is set to the ‘L’ level before time t0.Therefore, the MOS transistor 23 is turned off. Further, enable signalEN is set at the ‘L’ level. Therefore, the MOS transistor 71 is alsoturned off. As a result, the potentials of the nodes 1′2, N3 arerespectively maintained at voltage VREAD and voltage VREADLA.

(Time t0>

Next, enable signal EN is set to the ‘H’ level by means of the controlunit 60 at time to. Thus, the local pump 61 outputs a signal of ‘H’level to the gate of the MOS transistor 71. As a result, the MOStransistor 71 is turned on. In other words, the nodes N2 and N3 areshort-circuited. Then, signal TG output from the block decoder 20 of therow decoder 2 is set to the ‘H’ level to turn on the MOS transistor 23.Therefore, loads (parasitic capacitors of the word lines WL) are appliedto the output terminals of the first voltage generator circuit 41 andsecond voltage generator circuit 42. At this time, signal TG maintainsthe ‘H’ level after time t0. Therefore, the potentials of the nodes N2,N3 are temporarily set to 0 [V] from respective voltage VREAD andvoltage VREADLA generated from the first, second voltage generatorcircuits 41, 42.

Then, after time t0, the potentials of the nodes N2, N3 rise at the samerate in a period in which enable signal EN is kept at the ‘H’ level orin a period in which the MOS transistor 71 is kept in the on s=ate.Likewise, the potentials of the word lines WL connected to the nodes N2,N3 also rise at the same rate.

<Time t1>

When time t1 is reached, the potentials of the nodes N2, N3 and theunselected word lines WL are reached voltage VREAD. Then, the controller6 switches enable signal EN to the ‘L’ level. That is, an output of thelocal pump 61 is set to the ‘L’ level. As a result, the MOS transistor71 is turned off.

Therefore, the nodes N2 and N3 are electrically isolated. Therefore, thepotential of the node N2 is set to voltage VREAD and the potential ofthe unselected word line WL is maintained at voltage VREAD.

<After Time t1>

After time t1, the potential of the node N3 rises to voltage VREADLA.This is because the second voltage generator circuit 42 generatesvoltage VREADLA. That is, the potential of the unselected word line WLto which voltage VREADLA is transferred rises to voltage VREADLA aftertime t1.

<Voltage Transfer Operation at Read Operation Time (Second Case)>

Next, the voltage transfer operation of the NAND flash memory isexplained with reference to FIG. 8. FIG. 8 shows a case wherein voltageVREAD generated from the first voltage generator circuit 41 is higherthan voltage VREADLA. That is, voltage VREADLA=voltage (VREAD-α).Further, the explanation for the same operation as the read operation(first case) explained above is omitted.

As shown in FIG. 8, the potential of the node N3 rises at the samerising rate as the potential of the node N2 after time t0 like the caseof the above operation (first case). As described above, voltageVREAD>voltage VREADLA. Therefore, the controller 6 switches enablesignal EN to the ‘L’ level at time t1 at which the potentials of thenodes N2, N3 reach voltage VREADLA. That is, an output of the local pump61 is set to the ‘L’ level. As a result, the MOS transistor 71 is turnedoff and the nodes N2 and N3 are electrically isolated. Therefore, thepotential of the node N3 is maintained at voltage VREADLA. In otherwords, the potential of the unselected word line WL electricallyconnected via the node N3 is also maintained at voltage VREADLA.

After time t1, the potential of the node N2 rises to voltage VREAD. Thisis because the first voltage generator circuit 41 generates voltageVREAD. That is, the potential of the unselected word line WL to whichvoltage VREAD is transferred rises to voltage VREAD after time t1.

<Effect of this Embodiment>

In a semiconductor device and the control method for the semiconductordevice according to this embodiment, the effect (1) can be attained.

(1) Operation Reliability can be Enhanced:

The effect of this embodiment is explained below. In the semiconductordevice and the control method for the semiconductor device according tothis embodiment, the short circuit 7 that short-circuits the outputterminal (node N2) of the first voltage generator circuit 41 and theoutput terminal (node N3) of the second voltage generator circuit 42 andthe controller 6 that has a function of controlling the above circuitbased on time are provided as shown in FIG. 5. When explaining theeffect, for example, a case wherein the word line WL31 is used as theselected word line WL is considered like the above case.

According to this embodiment, the controller 6 short-circuits the outputterminals of the first voltage generator circuit 41 and second voltagegenerator circuit 42 as required. In the case of short-circuiting, theparasitic capacitors of the word lines WL0 to WL30 and word lines WL33to WL63 are applied as loads to the first voltage generator circuit 41and second voltage generator circuit 42. That is, the load of the firstvoltage generator circuit 41 is alleviated.

Further, it can be prevented that only the word line WL32 is dealt withas the load (parasitic capacitor) as viewed from the second voltagegenerator circuit 42 that outputs voltage VREADLA.

Therefore, for example, the rising rate of voltage VREADLA transferredto the word line WL32 can be suppressed from becoming higher than therising rate of voltage VREAD transferred to the word lines WL0 to WL30and word lines WL33 to WL63.

That is, in this embodiment, the controller 6 snort-circuitsshort-circuits the output terminal of the first voltage generatorcircuit 41 that generates voltage VREAD and the output terminal of thesecond voltage generator circuit 42 that generates voltage VREADLA in aperiod of (t1-t0). That is, as shown in FIG. 7 and FIG. 8, thepotentials of the nodes N2 and N3 that are the output terminals thereofare set to the same potential in the period (t1-t0). If the selectedword line WLN is WL31, the potentials of the word lines WL0 to WL30 andword lines WL32 to WL63 are set to the same potential. As a result, thepotentials of the word lines WL0 to WL30 and word lines WL32 to WL63rise at the same rising rate and then the potentials of the word linesWL0 to WL30 and word lines WL33 to WL63 are set to voltage VREAD aftertime t1.

That is, the controller 6 short-circuits the output terminal of thefirst voltage generator circuit 41 and the output terminal of the secondvoltage generator circuit 42 in a period of (t1-t0). Therefore, althoughthe potential of the word line WL32 is set to voltage VREADLA at acertain time t, the potentials of the word lines WL0 to WL30 and wordlines WL33 to WL63 are still kept at 0 [V] and occurrence of a potentialdifference between the word lines WL can be prevented. This is the sameeven if the number of word lines WL for each block BLK unit becomeslarger. Therefore, it is possible to solve a problem that, for example,only the potential of the word line WL32 is set to voltage VREADLA and,as a result, the potential of the n⁺-type impurity diffusion layer 103in the memory cell transistor MT whose control gate 107 is connected tothe word line WL32 is boosted and an abrupt potential difference occursbetween the n⁺-type impurity diffusion layer 103 and the control gate107 of the memory cell transistor MT corresponding to the word lineWL33.

Thus, a voltage approximately equal to voltage VREADLA will not beapplied between the n⁺-type impurity diffusion layer 103 whose potentialrises to a value near voltage VREADLA, for example, and the control gate107 functioning as the word line WL33. As a result, as shown in FIG. 9,a leakage current (GIDL) will not occur due to band-to-band tunneling ina portion in which the drain region and the control gate 107 functioningas the word line WL32 overlap.

As a result, the GIDL current will not occur and the operationreliability can be enhanced because the above voltages are transferredto the word lines WL.

Further, voltages are transferred to the word lines WL0 to WL30 and wordlines WL32 to WL63 of the selected block BLK by means of the first,second voltage generator circuits 41, 42 in the period (t1-t0). That is,the voltage driving ability (pumping ability) for loads of the wordlines WL0 to WL30 and word lines WL32 to WL63 can be enhanced byproviding the second voltage generator circuit 42 in addition to thefirst voltage generator circuit 41. Therefore, a time required forreaching voltage VREAD can be reduced in comparison with a case whereinthe potentials of the word lines WL0 to WL30 and word lines WL33 to WL63are charged to voltage VREAD only by means of the first voltagegenerator circuit 41. That is, as shown in FIG. 7 and FIG. 8, the timeis reduced from t′1 to (t1-t0), and therefore, the time required forshifting the operation to the data read operation (sense) by the senseamplifier 5 in the next operation can be reduced.

In this case, t′1 indicates a time required for the potentials of theword lines WL0 to WL30 and word lines WL33 to WL63 to reach voltageVREAD after the potential of the word line WL32 has reached voltageVREADLA in a case where the output terminals are not short-circuited.Further, it is supposed that the relationship of t′1>(t1-t0) is set.Thus, the operation speed of the whole circuit can be enhanced.

<Modification>

Next, a semiconductor device and the control method for thesemiconductor device according to a modification of the first embodimentis explained with reference to FIG. 10. FIG. 10 is a time chart forillustrating a voltage transfer operation at a read operation time in aNAND flash memory according to the modification.

FIG. 10 is a time chart showing enable signal EN supplied to the localpump 61, a potential applied to the gate of the MOS transistor 71,signal TG, the on·off state of the MOS transistor 23, potentials of thenodes N2, N3 and potentials of the word lines WL.

In the modification, a case of voltage VREAD>voltage VREADLA isexplained. That is, the relationship of voltage VREADLA=voltage(VREAD-α) is set. The timing of the voltage transfer operation iscontrolled by the controller 6. The same operation as the read operationexplained in the first embodiment is emitted omitted. Further, theselected word line WLN is set to WL31. That is, voltage VREADLA istransferred to the unselected word line WL32 and voltage VREAD istransferred to the other unselected word lines WL0 to WL30 andunselected word lines WL33 to WL63.

<Time t0 to t1>

As shown in FIG. 10, a signal supplied to the gate of the MOS transistor71 is set to the ‘L’ level by means of the controller 6 at time t1before the potentials of the nodes N2, N3 and word line WL reach voltageVREADLA. That is, enable signal EN supplied to the local pump 61 is setto the ‘L’ level by means of the control unit 60 at time t1. As aresult, the MOS transistor 71 is turned off and the nodes N2 and N3 areelectrically isolated.

Then, since the load for the second voltage venerator circuit 42 is setto the unselected word line WL32, the rising rate of voltage VREADLAgenerated from the second voltage generator circuit 42 is increased attime t1. That is, a voltage inclination is made abrupt.

<Time t2 to t3>

The potentials of the node N3 and unselected word line WL32 reachvoltage VREADLA at time t2. Then, the potentials of the unselected wordlines WL0 to WL30 and unselected word lines WL33 to WL63 reach voltageVREAD at time t3.

<Effect of Modification>

In the semiconductor device and the control method for the semiconductordevice according to the modification, the following effect (2) can beobtained in the case of voltage VREAD >voltage VREADLA.

(2) Operation Speed can be Enhanced:

In the semiconductor device and the control method for the semiconductordevice according to the modification, the controller 6 turns off the MOStransistor 71 at time t1 before the potential of the node N3 reachesvoltage VREADLA. As a result, the voltage transfer operation withrespect to the word line WL can be smoothly performed. This is becausethe MOS transistor 71 is not turned off immediately after the potentialof the node N3 has reached voltage VREADLA.

Therefore, it becomes possible to prevent the potentials of the node N3and word line WL32 from overshooting from voltage VREADLA immediatelyafter the MOS transistor 71 is turned off, that is, the nodes N2 and N3are electrically isolated.

Based on the above explanation, in the semiconductor device and thecontrol method for the semiconductor device according to themodification of this embodiment, the time required for a voltageovershooting from voltage VREADLA to return to voltage VREADLA can beprevented from being increased. Thus, the operation speed can beenhanced and the operation speed of the whole chip can be enhancedaccording to the semiconductor device of this embodiment.

[Second Embodiment]

Next, a semiconductor device and the control method for thesemiconductor device according to a second embodiment is explained. Thesemiconductor device according to the second embodiment further includesa sixth voltage generator circuit 46 that generates and outputs voltageVREADK. The explanation for the same configuration as that of the firstembodiment is omitted.

FIG. 11 is a block diagram of a voltage generator circuit 4 provided inthe semiconductor device according to this embodiment. In FIG. 11, thethird voltage generator circuit 43, fourth voltage generator circuit 44and fifth voltage generator circuit 45 are emitted omitted.

The voltage generator circuit 4 further includes the sixth voltagegenerator circuit 46 and short circuit 9 as shown in FIG. 11. A MOStransistor 91 functions as a short circuit. One end of the current pathof the MOS transistor 91 is connected to a node N3, the other endthereof is connected to a node N4 and the gate thereof is supplied witha signal from the controller 6. Therefore, the nodes N2, N3 and N4 areshort-circuited by causing the controller 6 to supply a signal of ‘H’level to the MOS transistor 91 in response to enable signal EN.

Further, the output terminal of the sixth voltage venerator circuit 46is connected to the node N4. The timing at which the ‘H’ level signal issupplied to the gate of the MOS transistor 91 is set at the same timingas in the case of the MOS transistor 71. As a result, the potentials ofthe nodes N2 to N4 are set to the same potential while the MOStransistors 71 and 91 are kept in the on state.

Further, the sixth voltage generator circuit 46 has the sameconfiguration as that of FIG. 4 in the first embodiment. That is, itgenerates voltage VREADK by controlling a value of the limiter 50.Voltage VREADK is a voltage that turns on the memory cell transistor MTand the magnitude thereof can be changed based on the thresholddistribution of the memory cell transistor MT like voltage VREADLA.

That is, voltage VREADK is set to voltage (VREAD+β) or voltage (VREAD-β)(voltages (VREAD-β) and voltage (VREAD+β) are hereinafter respectivelyreferred to as voltages VREADK⁻ and VREADK₊ as required). Values of αand β may be set to the same value or set to satisfy the relationship ofα>β or α<β. Further, voltage VREADK⁻ may be set to voltage (VREAD+β) asrequired. That is, in this case, voltage VREADK is always set higherthan voltage VREAD.

If the selected word line WL is set to an Nth word line in FIG. 1,voltage VREADK is a voltage to be transferred to the (N−1)th word lineWL or (N−1)th word line WL and (N+1)th word line WL.

The local pump 61 may use the potential of the node N4 as a referencevoltage in addition to the potential of the node N3. That is, if thethreshold voltage of the MOS transistor 91 is set to the same voltage asthreshold voltage Vth₇₁ of the MOS transistor 71, the local pump 61 mayuse the potential of the node N3 or N4 as a reference voltage and applythe potential of the sum of the reference voltage and Vth₇₁ to the gatesof the MOS transistors 71 and 91.

In a case where the threshold voltage of the MOS transistor 91 is set toVth₉₁, the local pump 61 may apply a voltage (potential of the node N3or N4+voltage Vth₉₁) to the gates of the MOS transistors 71 and 91 ifvoltage Vth₉₁>voltage Vth₇₁. Further, if voltage Vth₇₁>voltage Vth₉₁,the local pump 61 may apply a voltage (potential of the node N3 orN4+voltage Vth₇₁) to the gates of the MOS transistors 71 and 91.

If voltages Vth₇₁, Vth₉₁ are different from each other, the local pump61 may separately supply ‘H’ level signals to the gates of the MOStransistors 71 and 91. That is, the local pump 61 may apply a voltage(potential of the node N3 or N4+voltage Vth₉₁) to the gate of the MOStransistor 91 while applying a voltage (potential of the node N3 orN4+voltage Vth₇₁) to the gate of the MOS transistor 71.

<Read Operation of NAND Flash Memory>

Next, first and second cases of the read operation by use of voltagesVCGR, VREAD, VREADLA and VREADK in the NAND flash memory are explainedwith reference to FIG. 12A, FIG. 12B and FIG. 13.

<First Case of Read Operation>

First, the first case of the read operation is explained with referenceFIG. 12A, FIG. 12B. In the first case of the read operation, a casewhere voltage VREADK is transferred only to the word line WL(N−1) whenvoltage VCGR is transferred to the selected word line WLN is explained.In this case, voltage VREADLA is transferred to the word line WL(N+1).Since the read method for the selected word line WLN and unselected wordline WL(N+1) is the same as that in the first embodiment, theexplanation thereof is omitted.

<Step 1>

As shown in FIG. 12A, the first voltage generator circuit 41 transfersvoltage VREAD to the word line WL(N−3) to word line WLN, word lineWL(N+2) and word line WL(N+3). Further, the sixth voltage generatorcircuit 46 transfers voltage VREAD to the word line WL(N−1).

<Step 2>

As shown in FIG. 12B, the sixth voltage generator circuit 46 transfersvoltage VREADK to the word line WL(N−1). As a result, the memory celltransistors MT connected to the word lines WL(N−3) to WL(N+3) are turnedon to permit the sense amplifier 5 to perform the data read operationvia a bit line BL (not shown).

<Second Case of Read Operation>

Next, a case wherein voltage VREADK is transferred to the word lineWL(N−1) and word line WL(N+1) is explained with reference to FIG. 13.FIG. 13 shows a state in which data is read from the memory cellcorresponding to the selected word line WLN after step 1 of FIG. 12.That is, the third voltage generator circuit 43 transistors voltage VCGRto the word line WLN.

As shown in FIG. 13, voltage VREADK is transferred to the word linesWL(N−1) and WL(N+1). As described before, voltage VREADK is set toeither voltage VREADK⁻ or voltage VREADK₊. That is, voltage VREADK istransferred to the word line WL(N−1) and word line WL(N+1) by the numberof times corresponding to the number of cases.

The memory cell transistors MT whose control gates 107 are applied withvoltages VREADK, VREAD and VCGR are turned on. As a result, channels areformed directly below the memory cell transistors MT connected to theword lines WL(N−3) to WL(N+3) and the sense amplifier 5 performs thedata read operation via the bit line BL (not shown).

<Magnitude Relationship between Voltage VREAD, Voltage VREADLA andVoltage VREADK>

Next, the magnitude relationship between voltages generated from thefirst voltage generator circuit 41, second voltage generator circuit 42and sixth voltage generator circuit 46 is explained. The magnituderelationship between voltages generated from the first voltage generatorcircuit 41, second voltage generator circuit 42 and sixth voltagegenerator circuit 46 is divided into the following five patterns (I) to(V). In this case, the relationships at the data read operation times inFIG. 12A and FIG. 12B are set to (I) to (V) and the data read voltagerelationships in FIG. 13 are set to (VI) and (VII).

(I) Voltage VREAD≤voltage VREADLA≤voltage VREADK

(II) Voltage VREADK≤voltage VREAD≤voltage VREADLA

(III) Voltage VREADLA23 VREADLA≤voltage VREAD≤voltage VREADK

(IV) Voltage VREADK≤voltage VREADLA≤voltage VREAD

(V) Voltage VREAD≤voltage VREADK≤voltage VREADLA

(VI) Voltage VREADK⁻<voltage VREAD <voltage VREADK₊

(VII) Voltage VREAD≤voltage VREADK⁻≤voltage VREADK₊

<Voltage Transfer Operation at Read Operation Time (Third Case)>

Next, the voltage transfer operation at the read operation time in theNAND flash memory explained above is explained with reference to FIG.14. FIG. 14 is a time chart of enable signal EN supplied to the localpump 61, a potential applied to the gate of the MOS transistor 71,potentials of the nodes N2, N3 and potentials of the word lines WL. Thetimings of the voltage transfer operations are controlled by thecontroller 6. In this case, the potentials of the nodes N2, N3 in thecase (I) are raised as one example. Further, the explanation for thesame operation as the read operation (first and second cases) explainedabove is omitted.

<Before Time t0>

As shown in FIG. 14, signal TG is set to the ‘L’ level to turn off theMOS transistor 23 before time t0 and the potentials of the nodes N2 toN4 are respectively set to voltages VREAD, VREADLA and VREADK.

(Time t0 to t1>

After time t0, the MOS transistors 71, 91 are turned on to short-circuitthe nodes N2 to N4. Further, since signal TG is set at the ‘H’ level,the MOS transistor 23 is turned on, that is, the load (parasiticcapacitor of the word line WL) and the nodes N2 to N4 are electricallyconnected. Therefore, output voltages of the first, second and sixthvoltage generator circuits 41, 42 and 46 are temporarily reduced andthen the potentials of the nodes N2 to N4 rise at the same rising rate.

When time t1 is reached, the controller 6 switches enable signal EN tothe ‘L’ level. That is, an output of the local pump 61 is set to the ‘L’level. At this time, since the relationship of voltage VREAD voltageVREADLA <voltage VREADK is set, the controller 6 controls time to setthe potentials of the nodes N2 to N4 to voltage VREAD at time t1.Further, at this time, the potential of the word line WL is set tovoltage VREAD.

Since the MOS transistors 71, 91 are simultaneously turned off at timet1, the nodes N2 to N4 are electrically isolated.

<Time t1 to t3>

The potential of the node N3 reaches voltage VREADLA at time t2. Forexample, if the selected word line WLN is set to WL31, the potential ofa word line WL32 adjacent to the selected word line WL31 reaches voltageVREADLA.

Further, the potential of a word line WL30 and the potential of the nodeN4 reach voltage VREADK at time t3.

The voltage transfer operation in the case (I) is explained above, butthe same operation is performed in the cases (II) to (V). That is, thecontroller 6 maintains the on state of the MOS transistors 71 and 91 toshort-circuit the nodes N2 to N4 until the potential one of the nodes N2to N4 reaches one of voltages VREAD, VREADLA and VREADK.

After this, when the potential of one of the nodes N2 to N4 reaches oneof the above voltages, the MOS transistors 71, 91 are turned off. Then,the potential of the node whose potential does not reach a desiredvoltage rises to a voltage generated front the voltage generator circuit4.

<Effect of this Embodiment>

In the semiconductor device and the control method for the semiconductordevice according to this embodiment, the effect (1) can be attained.That is, the operation reliability of the semiconductor device can beenhanced. In the semiconductor device and the control method for thesemiconductor device according to this embodiment, the potentials of theword lines WL to which voltages VREADLA, VREADK and VREAD aretransferred rise at the same rising rate even when voltage VREADK istransferred to the word line WL in addition to voltage VREADLA explainedin the first embodiment. Therefore, there occurs no problem that a timelag occurs in the potential rising operation of the word line WL as inthe conventional case explained in the first embodiment. That is, in thesemiconductor device according to this embodiment, a GIDL current can besuppressed and the operation reliability can be enhanced.

If one of voltages VREADLA and VREADK is higher than voltage VREAD, thecontroller 6 performs the operation explained in the modification toattain the effect (2). That is, also, in this embodiment, enable signalEN is switched to the ‘L’ level to turn off the MOS transistors 71, 91before the potentials of the nodes N2 to N4 reach one of voltagesVREADLA and VREADK in the cases (II), (III) and (IV). As a result, thevoltage transfer operation with respect to the word line WL can besmoothly performed and a problem that an operation delay occurs due toovershooting from a desired voltage can be avoided.

Further, in the semiconductor device according to this embodiment, thecontroller 6 transfers the sum of the threshold voltages of the MOStransistors 71, 91 and a second voltage to the gates of the MOStransistors 71 and 91 while monitoring the second potential of thesecond node.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: a firstvoltage generator circuit which outputs a first voltage to a first node;a second voltage generator circuit which outputs a second voltage to asecond node; a third voltage generator circuit which outputs a thirdvoltage to a third node; a first MOS transistor capable ofshort-circuiting the first node and the second node; a second MOStransistor capable of short-circuiting the second node and the thirdnode; and a controller which performs a control operation toshort-circuit the first node and the second node by turning on the firstMOS transistor, controlling a length of a period in which the first MOStransistor is kept in an on ON state based on time, wherein thecontroller simultaneously performs on and off switching operations ofthe first MOS transistor and second MOS transistor.
 2. The deviceaccording to claim 1, wherein a first load is connected to the firstnode, and a second load larger than the first load is connected to thesecond node, and whenif a potential of the first load reaches the secondvoltage in a case whereand the first voltage is higher than the secondvoltage atduring a read timeoperation, the controller turns off thefirst MOS transistor.
 3. The device according to claim 1, wherein afirst load is connected to the first node, and a second load larger thanthe first load is connected to the second node, and in a case whereifthe second voltage is higher than the first voltage atduring a readtimeoperation, the controller turns off the first MOS transistor beforea potential of the second load reaches the first voltage.
 4. The deviceaccording to claim 1, wherein the first MOS transistor is one of ann-type intrinsic MOS transistor, a depression-type MOS transistor, andan enhancement-type MOS transistor.
 5. The device according to claim 1,wherein the controller senses a potential of the second node, andtransfersoutputs a voltage equal to the sum of the above potential and athreshold voltage of the first MOS transistor to the gate of the firstMOS transistor.
 6. The device according to claim 1, further comprising:a third voltage generator circuit which outputs a third voltage to athird node; and a second MOS transistor capable of short-circuiting thesecond node and the third node, wherein the controller simultaneouslyperforms on and off switching operations of the first MOS transistor andsecond MOS transistor.
 7. The device according to claim 6 1, wherein thecontroller senses a potential of one of the second node and the thirdnode, and transfers outputs to the gates of the first and second MOStransistors one of (a) a first voltage equal to the sum of the abovepotential and a first threshold voltage of the first MOS transistor, and(b) a second voltage equal to the sum of the above potential and asecond threshold voltage of the second MOS transistor to the gates ofthe first and second MOS transistors.
 8. The device according to claim1, further comprising: a memory cell array including plural memory cellswhose current paths are serially connected and, each of which includesthe memory cells including a charge storage layer and control gate; andword lines connected to the control gates of the memory cells and, eachof the word lines being used as one of the first and second loads;wherein the first and second voltage generator circuits transfer one ofthe first and second voltages to the word lines.
 9. A semiconductordevice comprising: a memory cell array including i memory cells (whereini is an integral number larger than 2) capable of holding data each ofwhich includes a charge storage layer and control gate and the i memorycells are serially connected along a current path; and a voltagegenerator circuit which generates a first voltage and a second voltage,transferring the first and the second voltages to word lines connectedto the control gates of the memory cells, wherein the voltage generatorcircuit transfersoutputs the first voltage to the word line connected tothe control gate of a jth one of the ith memory cellcells, andtransfersoutputs the second voltage to the word lines connected to thecontrol gates of the (i+1)th and (i+2)th(j+1) and (j+2)th memory cellswhich are arranged on a drain side of the ithjth memory cell.
 10. Thedevice according to claim 9, wherein the first voltage is a voltagecorresponding to data held by the ith jth memory cell.
 11. The deviceaccording to claim 9, further comprising: a MOS transistor capable ofshort-circuiting a first node and a second node; and a controller whichperforms a control operation to turn on the MOS transistor toshort-circuit the first node and the second node, wherein the voltagegenerator circuit includes a first voltage generator circuit whichgenerates the first voltage and outputs the first voltage to the firstnode, and a second voltage generator circuit which generates the secondvoltage and outputs the second voltage to the second node, and thecontroller controls a length of a period in which the MOS transistor ismaintained in an on ON state based on time.
 12. The device according toclaim 11, wherein the controller senses a potential of the second node,and transfersoutputs a voltage equal to the sum of the above potentialand a threshold voltage of the MOS transistor to the gate of the MOStransistor.
 13. The device according to claim 9, wherein the MOStransistor is one of an n-type intrinsic MOS transistor, adepression-type MOS transistor, and an enhancement-type MOS transistor.14. The device according to claim 11, wherein a word line used as afirst load is connected to the first node, and a word line used as asecond load larger than the first load is connected to the second node,and in a case whereif the second voltage is higher than the firstvoltage, the controller turns off the first MOS transistor before apotential of the second load reaches the first voltage.
 15. A controlmethod of a semiconductor device comprising: causing a first voltagegenerator circuit to generate a first voltage and output the firstvoltage to a first node; causing a second voltage generator circuit togenerate a second voltage and output the second voltage to a secondnode; causing a third voltage generator circuit to generate a thirdvoltage and output the third voltage to a third node; causing acontroller to set a first MOS transistor in an on ON state andshort-circuit the first node and the second node; causing a controllerto set a second MOS transistor in an ON state and short-circuit thesecond node and third node; causing the controller to turn on the firstand second MOS transistors and short-circuit the first, second and thirdnodes; causing the controller to simultaneously perform on and offswitching operations of the first and second MOS transistors; andcausing the controller to control a length of a period in which thefirst MOS transistor is maintained in the on ON state based on time. 16.The method according to claim 15, further comprising: causing the firstvoltage generator circuit to transfer output the first voltage to afirst load via the first node; causing the second voltage generatorcircuit to transfer output the second voltage higher than the firstvoltage to a second load larger than the first load via the second node;and causing the controller to turn off the first MOS transistor before apotential of the second load reaches the first voltage.
 17. The methodaccording to claim 15, further comprising: causing the first voltagegenerator circuit to transfer output the first voltage to a first loadvia the first node; causing the second voltage generator circuit totransfer output the second voltage to a second load larger than thefirst load via the second node; and if the first voltage is higher thanthe second voltage at during a read time operation, causing thecontroller to turn off the first MOS transistor at the timing of when apotential of the first load reaching reaches the second voltage.
 18. Themethod according to claim 15, further comprising: causing the controllerto sense a potential of the second node; and causing the controller totransfer output a voltage equal to the sum of the above potential and athreshold voltage of the first MOS transistor to the gate of the firstMOS transistor.
 19. The method according to claim 15, furthercomprising: causing a third voltage generator circuit to generate athird voltage and output the third voltage to a third node; causing thecontroller to turn on the first and second MOS transistors andshort-circuit the first to third nodes; and causing the controller tosimultaneously perform on and off switching operations of the first andsecond MOS transistors.
 20. The method according to claim 16, furthercomprising: transferringoutputting the first voltage to a control gateof an ith memory cell among plural memory cells whose current paths areserially connected via the first node atduring a data readtimeoperation; and transferring the second voltage to a control gate ofan (i+1)th memory cell arranged on a drain side of the ith memory cellvia the second node.
 21. A semiconductor device comprising: a firstvoltage generator including a first charge pump, the first voltagegenerator being configured capable of outputting a first read voltage toa first node; a second voltage generator including a second charge pump,the second voltage generator being configured capable of outputting asecond read voltage different from the first read voltage to a secondnode; a third voltage generator including a third charge pump, the thirdvoltage generator being configured capable of outputting a third readvoltage different from each of the first and second read voltages to athird node; a first MOS transistor configured capable ofshort-circuiting the first node and the second node; a second MOStransistor configured capable of short-circuiting the second node andthe third node; and a first controller configured capable of performinga control operation, the first controller being configured to turn onthe first MOS transistor and the second MOS transistor in the controloperation, wherein the first, second and third read voltages are each avoltage sufficient to turn on a memory transistor.
 22. The semiconductordevice according to claim 21, wherein the first voltage generatorincludes a first charge pump controller and the second voltage generatorincludes a second charge pump controller.
 23. The semiconductor deviceaccording to claim 21, wherein the first MOS transistor is a MOStransistor with a high withstand voltage.
 24. The semiconductor deviceaccording to claim 21, wherein the first controller is configuredcapable of short-circuiting the second node and third node by turning onthe second MOS transistor in the control operation.
 25. Thesemiconductor device according to claim 21, wherein an input node of thefirst charge pump is electrically connected to an output node of thefirst charge pump controller and an input node of the first charge pumpcontroller is electrically connected to an output node of the firstcharge pump.
 26. The semiconductor device according to claim 25, whereinan input node of the second charge pump is electrically connected to anoutput node of the second charge pump controller and an input node ofthe second charge pump controller is electrically connected to an outputnode of the second charge pump.
 27. The semiconductor device accordingto claim 21, wherein an input node of the third charge pump iselectrically connected to an output node of the third charge pumpcontroller and an input node of the third charge pump controller iselectrically connected to an output node of the third charge pump.
 28. Asemiconductor device comprising: a first voltage generator including afirst charge pump, the first voltage generator being configured tooutput a first voltage to a first node; a second voltage generatorincluding a second charge pump, the second voltage generator beingconfigured to output a second voltage to a second node; a third voltagegenerator including a third charge pump, the third voltage generatorbeing configured to output a third voltage to a third node; a first MOStransistor configured to short-circuit the first node and the secondnode; a second MOS transistor configured to short-circuit the secondnode and the third node; and a first controller configured capable ofperforming a control operation, the first controller being configured toshort-circuit the first node and second node at by turning on the firstMOS transistor in the control operation.
 29. The semiconductor deviceaccording to claim 28, further comprising: the first controller beingconfigured to short-circuit the second node and third node by turning onthe second MOS transistor.
 30. The semiconductor device according toclaim 28, wherein the first voltage generator includes a first chargepump controller, the second voltage generator includes a second chargepump controller and the third voltage generator includes a third chargepump controller.
 31. The semiconductor device according to claim 28,wherein the first MOS transistor is a MOS transistor with a highwithstand voltage.
 32. The semiconductor device according to claim 29,wherein the first controller is configured to short-circuit the firstnode, second node and third node by turning on the first and second MOStransistors in the control operation.
 33. The semiconductor deviceaccording to claim 29, wherein an input node of the first charge pump iselectrically connected to an output node of the first charge pumpcontroller and an input node of the first charge pump controller iselectrically connected to an output node of the first charge pump.
 34. Asemiconductor device comprising: a first voltage generator including afirst charge pump, the first voltage generator being configured capableof outputting a first voltage to a first node; a second voltagegenerator including a second charge pump, the second voltage generatorbeing configured capable of outputting a second voltage to a secondnode; a third voltage generator including a third charge pump, the thirdvoltage generator being configured capable of outputting a third voltageto a third node; a first MOS transistor configured capable ofshort-circuiting the first node and the second node; a second MOStransistor configured capable of short-circuiting the second node andthe third node; and means for performing a control operation toshort-circuit the first node and the second node by turning on the firstMOS transistor.
 35. The semiconductor device according to claim 34,wherein the means for performing is configured to short-circuit thefirst node to the second node during rising voltage of either the firstnode or the second node.
 36. The semiconductor device according to claim34, wherein at least one of the first voltage and the second voltage arerising when the first node is connected to the second node.
 37. Thesemiconductor device according to claim 34, wherein the first voltagegenerator includes a first charge pump controller and the second voltagegenerator includes a second charge pump controller.
 38. Thesemiconductor device according to claim 34, wherein the first MOStransistor is a MOS transistor with a high withstand voltage.
 39. Thesemiconductor device according to claim 34, wherein the means forperforming is also configured to turn on the second MOS transistor sothat the second node is short-circuited to the third node.
 40. Thesemiconductor device according to claim 39, wherein the means forperforming is configured to short-circuit the second node to the thirdnode during rising voltage of at least one of the first node, the secondnode, and the third node.
 41. The semiconductor device according toclaim 39, wherein at least one of the first voltage, the second voltage,and the third voltage is rising when the second node is connected to thethird node.
 42. A semiconductor device comprising: a first voltagegenerator including a first charge pump, the first voltage generatorbeing configured capable of outputting a first voltage to a first node;a second voltage generator including a second charge pump, the secondvoltage generator being configured capable of outputting a secondvoltage to a second node; a third voltage generator including a thirdcharge pump, the third voltage generator being configured capable ofoutputting a third voltage to a third node; a first MOS transistordisposed between the first and second nodes; a second MOS transistordisposed between the first and second nodes; means for performing afirst control operation to short-circuit the first node and the secondnode by turning on the first MOS transistor; and means for performing asecond control operation to short-circuit the second node and the thirdnode by turning on the second MOS transistor.